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W948D6FB / W948D2FB
256Mb Mobile LPDDR
7.6.13 Interrupting Write to Precharge
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in figure below.
Note that only data-in pairs that are registered prior to the t WR period are written to the internal array, and any
subsequent data-in should be masked with DM, as shown in figure. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until t RP is met.
CK
CK
Command
WRITE
NOP
NOP
NOP
PRE
NOP
Address
BA,Col b
BA,Col n
BA a(or
all)
DQS
DQ
t DQSSmax
DI b
t WR
*2
DM
*1
*1
*1
*1
1) Dl b = Data in to column b.
= Don't Care
2) An interrupted burst of 4, 8 or 16 is shown, 2 data elements are written.
3) t WR is referenced from the positive clock edge after the last desired Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) *1=can be Don't Care for programmed burst length of 4
6) *2=for programmed burst length of 4, DQS becomes Don't Care at this point
7.7 Precharge
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access a specified time (t RP ) after the PRECHARGE command is
issued.
Input A10 determines whether one or all banks are to be precharged. In case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don?t Care”.
Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE
command being issued. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if
the previously open row is already in the process of precharging.
Publication Release Date : Oct, 15, 2012
- 39 -
Revision : A01-004
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功能描述:IC LPDDR SDRAM 256MBIT 60VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:4G（256M x 16） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP I 包装:Digi-Reel® 其它名称:557-1461-6